Display device and driving circuit for displaying

ABSTRACT

A frame memory  105  stores the original image data received from a higher-level device  102  via an interface  103.  Color reduction processing means receives color reduction rate data through a transfer from an upper-level device  102  or manual setting means such as a switch or jumper settings. Based on this color reduction rate data, the number of colors in the gradation data of the original image is reduced, and the color count of the original image is simulated using the reduced color count. Also included are a timing generating circuit  106  and a gradation voltage generating circuit  107.  A gradation voltage selector  108  performs a partial halting of driver operations based on the color reduction rate.

BACKGROUND ART

[0001] The present invention relates to a panel-type display device thatcontrols display luminance through an applied voltage. Morespecifically, the present invention relates to a technology for displaydevices and display device driver circuits that lowers power consumptionrequirements by controlling the number of colors to be displayed.

[0002] An example of a technology that lowers power consumptionrequirements by using the applied voltage to control display luminanceis the display device described in “Asia display/IDW '01 proceedings”(p. 1583-1586, ITE/SID Publications). This display device performs colorreduction by dithering incoming gradation data, thus simulating thenumber of colors in the original gradation data (hereinafter alsoreferred to as the real color count) with a smaller number of colors. Asa result, power consumption is lower than when the real color count isdirectly displayed.

[0003] Color reduction operations such as dithering generally allowselection of the degree to which the color count is reduced from thereal color count (hereinafter referred to as the color reduction rate).There is less image degradation with smaller color reduction rates(close to the real color count) and more image degradation with largercolor reduction rates. On the other hand, a smaller number of colors todisplay means that the display device circuitry has less to do, thusallowing power consumption to be reduced.

[0004] As a result, different implementations are possible depending onthe usage of the display device, e.g., high-quality displays with littlecolor reduction and low-power displays with more color reduction.However, the color reduction rates in the conventional technologies havebeen constant (262,144 colors to 4096 colors). Thus, this type of usagehas not been considered.

SUMMARY OF THE INVENTION

[0005] The object of the present invention is to provide a displaydevice and driver circuit for the same in which the color count of anoriginal image received from a higher-level device is reduced and powerconsumption is limited based on this reduction so that longer operationis possible.

[0006] The present invention allows images to be displayed using aplurality of color reduction rates and also allows color reduction ratesto be selected externally through transfer from a higher-level device(e.g., a CPU), or by using manual setting means such as a switch orjumper settings. To implement these features, a display device accordingto the present invention adds the following to a conventional displaydevice: color reduction processing means reducing the color count ofgradation data in an original image based on color reduction rate dataindicating a color reduction rate, and virtually representing the colorcount of the original image using the reduced color count; and means forpartially stopping operations of the driver circuit based on the colorreduction rate.

[0007] The present invention provides a display device and a displaydevice driver circuit that controls display luminance based on appliedvoltages wherein: color reduction rate data is received from outside;the number of colors shown on the display is selected based on thiscolor reduction rate data; and unnecessary driver circuits are stoppedbased on the number of displayed colors. As a result, the power consumedby the display device can be reduced. Also, it is possible to selectbetween a high-quality mode with less color count reduction and alow-power mode with more color count reduction. As a result, a displaydevice that is convenient to use can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a block diagram for the purpose of describing a displaydevice driver circuit according to a first embodiment of a displaydevice of the present invention.

[0009]FIG. 2 is a drawing for the purpose of describing an interfaceinput signal according to the first embodiment of the present invention.

[0010]FIG. 3 is a timing chart illustrating the operations of theinterface input signal according to the first embodiment of the presentinvention.

[0011]FIG. 4 is a drawing for the purpose of describing the interfaceinput signal in the first embodiment.

[0012]FIG. 5 is a drawing for the purpose of describing the interfaceinput signal according to the first embodiment of the present invention.

[0013]FIG. 6 is a drawing for the purpose of describing color reductionrate data according to the first embodiment of the present invention.

[0014]FIG. 7 is a drawing for the purpose of describing the principlesinvolved in the dithering system of the first embodiment of the presentinvention.

[0015]FIG. 8 is a block diagram showing the structure of a ditherprocessing module according to the first embodiment of the presentinvention.

[0016]FIG. 9 is a drawing for the purpose of describing the operationsperformed by a dither signal generating module according to the firstembodiment of the present invention.

[0017]FIG. 10 is a drawing for the purpose of describing operationsperformed by the dither signal generating module according to the firstembodiment of the present invention.

[0018]FIG. 11 is a block diagram showing the structure of the dataconverter according to the first embodiment of the present invention.

[0019]FIG. 12 is a drawing for the purpose of describing the operationsperformed by a dither signal selector according to the first embodimentof the present invention.

[0020]FIG. 13 is a drawing for the purpose of describing the operationsperformed by the bit operation module A according to the firstembodiment of the present invention.

[0021]FIG. 14 is a drawing for the purpose of describing the operationsof the bit operation module B according to the first embodiment of thepresent invention.

[0022]FIG. 15 is a drawing for the purpose of describing the operationsof the dither processing module of the first embodiment of the presentinvention.

[0023]FIG. 16 is a drawing for the purpose of describing operationsperformed by the dither processing module according to the firstembodiment of the present invention.

[0024]FIG. 17 is a circuit diagram for the purpose of describing thestructure of the gradation voltage generating module according to thefirst embodiment of the present invention.

[0025]FIG. 18 is a drawing illustrating the operation of the gradationvoltage generating module according to the first embodiment of thepresent invention.

[0026]FIG. 19 is a block diagram showing the structure of a gradationvoltage selector according to the first embodiment of the presentinvention.

[0027]FIG. 20 is a timing chart for the purpose of describing theoperations performed by the gradation voltage selector according to thefirst embodiment of the present invention.

[0028]FIG. 21 is a drawing for the purpose of describing the operationsof a selector according to the first embodiment of the presentinvention.

[0029]FIG. 22 is an equivalent circuit illustrating the structure of thepixel module according to the first embodiment of the present invention.

[0030]FIG. 23 is a timing chart that illustrates the operationsperformed in the peripheral circuits according to the first embodimentof the present invention.

[0031]FIG. 24 is a block diagram showing the structure of a displaydevice driver circuit according to the second embodiment of the displaydevice of the present invention.

[0032]FIG. 25 is a drawing illustrating principles involved in an FRCsystem according to the second embodiment of the present invention.

[0033]FIG. 26 is a drawing illustrating color reduction rate dataaccording to the second embodiment of the present invention.

[0034]FIG. 27 is a block diagram showing the structure of an FRCprocessing module according to the second embodiment of the presentinvention.

[0035]FIG. 28 is a block diagram showing the structure of an FRC signalgenerating module according to the second embodiment of the presentinvention.

[0036]FIG. 29 is a timing chart illustrating the operations performed bythe FRC signal generating module according to the second embodiment ofthe present invention.

[0037]FIG. 30 is a drawing illustrating the operations performed by theFRC signal generating module according to the second embodiment.

[0038]FIG. 31 is a block diagram showing the structure of a dataconversion module according to the second embodiment of the presentinvention.

[0039]FIG. 32 is a drawing illustrating the operations of the bitoperation module A according to the second embodiment of the presentinvention.

[0040]FIG. 33 is a drawing describing the operation of the bit operationmodule B according to the second embodiment.

[0041]FIG. 34 is a block diagram showing the structure of a displaydevice driver circuit according to the second embodiment of the presentinvention.

[0042]FIG. 35 is a block diagram showing the structure of a displaydevice driver circuit according to the second embodiment of the presentinvention.

[0043]FIG. 36 is a block diagram showing the structure of a displaydevice driver circuit according to the third embodiment of the displaydevice of the present invention.

[0044]FIG. 37 is a timing chart for input signals in the thirdembodiment of the present invention.

[0045]FIG. 38 is a block diagram showing the structure of a ditherprocessing module according to the third embodiment of the presentinvention.

[0046]FIG. 39 is a block diagram showing the structure of a dithersignal generating module according to the third embodiment of thepresent invention.

[0047]FIG. 40 is a block diagram showing the structure of a gradationvoltage selector according to the third embodiment of the presentinvention.

[0048]FIG. 41 is a timing chart illustrating the operations performed bythe gradation voltage selector of the third embodiment of the presentinvention.

[0049]FIG. 42 is a block diagram showing the structure of a displaydevice according to the fourth embodiment of the present invention.

[0050]FIG. 43 is a block diagram showing the structure of a displaydevice according to the fourth embodiment of the present invention.

[0051]FIG. 44 is a block diagram showing the structure of a displaydevice according to the fourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION

[0052] The embodiments of the present invention will be described indetail using the drawings of the embodiments. First, a first embodimentof the present invention will be described using FIG. 1 through FIG. 23.

[0053]FIG. 1 is a block diagram for the purpose of describing a displaydevice driver circuit according to a first embodiment of a displaydevice of the present invention. FIG. 1 shows: a data line driver 101; aCPU 102; an interface 103; a dither processing module 104; a framememory 105; a timing generating module 106; a gradation voltagegenerating module 107; a gradation voltage selector; and an pixel module109. FIG. 2 is a drawing for the purpose of describing an interfaceinput signal according to a first embodiment of the present invention.FIG. 3 is a timing chart illustrating the operations of the interfaceinput signal according to the first embodiment of the present invention.

[0054] In this embodiment of the present invention, the pixel module 109can be, for example, a TFT liquid crystal. A gradation voltage based ongradation data is output by the data line driver module 101 to the pixelmodule 109 to provide multi-color displaying. In this embodiment, thegradation data received by the display device is digital data withsix-bits each assigned to R (red), G (green), B (blue). One pixel hascolor information corresponding to 262,144 colors.

[0055] First, the operations performed by the data line driver module101 will be described. A signal relating to displaying is sent by theCPU 102 to the data line driver module 101. This signal includesgradation data indicating how concentrated the colors are an addressindicating a display position, and color reduction rate data, which is acharacteristic of the present invention. The signals used by the CPU 102and the interface 103 are shown in FIG. 2 and include an RS signal forselecting address/gradation data, a WR signal for instructing a writeoperation, and a D signal containing the actual address/gradation datavalues.

[0056] As shown in FIG. 3, these signals involve an address cycle and agradation data write cycle. For example, in the addressing cycle, the Dsignal is set to a predetermined address when the RS signal is “low”.Then, the operation is executed when the WR signal is set to “low”. Inthe gradation data write cycle, the RS signal is “high” and the [?D?]signal is set to a predetermined gradation data value. Then, when the WRsignal is set to “low”, the operation is executed. These operations areprogrammed ahead of time in application software and the operatingsystem used to control the entire device. Next, a description of the Dsignal is provided in FIG. 4.

[0057]FIG. 4 is a drawing for the purpose of describing the interfaceinput signal in the first embodiment. As shown in FIG. 4, the D signal,which is used for the actual address/gradation data values, is an 18-bitsignal. In addressing cycles, the D signal contains the horizontal andvertical address (8 bits each) and, in gradation data write cycles, theD signal contains the RGB gradation data (6 bits each). FIG. 5 is adrawing for the purpose of describing the interface input signalaccording to the first embodiment of the present invention. A sampleimage transferred by this interface is shown. The interface 103 decodesthe display signal transferred from the CPU and outputs addresses andgradation data separately.

[0058]FIG. 6 is a drawing for the purpose of describing color reductionrate data according to the first embodiment of the present invention.The dithering processing module 104 in FIG. 1 receives gradation data,addresses, and color reduction rate data, performs color reductionthrough dithering, and outputs the results as reduced-color gradationdata. The color reduction rate data is 2-bit data that can indicatethree color reduction rates. As shown in FIG. 6, the value indicates howmany bits of the RGB gradation data input (6 bits each) are to bedithered.

[0059]FIG. 7 is a drawing for the purpose of describing the principlesinvolved in the dithering system of the first embodiment of the presentinvention. Dithering is a technique in which existing colors arecombined in space to generate intermediate colors. FIG. 7 shows sampleimages corresponding to the different color reduction rates. Next, thestructure and operations of the dither processing module 104 will bedescribed using FIG. 8 through FIG. 14.

[0060]FIG. 8 is a block diagram showing the structure of a ditherprocessing module according to the first embodiment of the presentinvention. FIG. 9 is a drawing for the purpose of describing theoperations performed by a dither signal generating module according tothe first embodiment of the present invention. In FIG. 8, the ditherprocessing module 104 includes a dither signal generating module 801 andR, G, B data conversion modules 802, 803, 804. As shown in FIG. 9, thedither signal generating module 801 generates four types of dithersignals A-D based on the lowest bit of the received horizontal andvertical addresses.

[0061]FIG. 10 is a drawing for the purpose of describing operationsperformed by the dither signal generating module according to the firstembodiment of the present invention. FIG. 10 shows dither signal valuescorresponding to an actual screen. This example is equivalent to thecombination patterns of existing colors shown in FIG. 7. FIG. 11 is ablock diagram showing the structure of the data converter according tothe first embodiment of the present invention. As shown in FIG. 11, thedata converter 802 includes a dither signal selector 1101, a bitoperation module A 1102, a subtractor 1103, and a bit operation module B1104. FIG. 11 simply shows “bit operation A” and “bit operation B”.

[0062]FIG. 12 is a drawing for the purpose of describing the operationsperformed by a dither signal selector according to the first embodimentof the present invention. The dither signal selector 1101 in FIG. 11selects and outputs one signal out of the dither signals A-D based onthe lowest two bits of the 6-bit gradation data. The selected dithersignal varies according to the color reduction rate data. Thisrelationship is shown in FIG. 12.

[0063]FIG. 13 is a drawing for the purpose of describing the operationsperformed by the bit operation module A according to the firstembodiment of the present invention. The bit operation module A 1102adds a “0” to the selected dither signal to generate 6-bit data, but howthe “0” gets added differs depending on the color reduction rate data.This relationship is shown in FIG. 13. The purpose of this bit operationis to ease the subtraction operation performed at the next step. Also,the output value from the bit operation module A is varied based on thehigher level bit values of the gradation data to prevent the subtractionresult from becoming negative.

[0064]FIG. 14 is a drawing for the purpose of describing the operationsof the bit operation module B according to the first embodiment of thepresent invention. FIG. 15 is a drawing for the purpose of describingthe operations of the dither processing module of the first embodimentof the present invention. The subtractor 1103 subtracts the output ofthe bit operation module A from the gradation data and outputs theresult. As shown in FIG. 14, the bit operation module B 1104 rearrangesthe gradation data bits based on the color reduction rate data, and theresults are output as the reduced-color gradation data.

[0065] With this dithering operation, the gradation data input isconverted to the reduced-color gradation data shown in FIG. 15. In FIG.15, the crosshatched sections indicate that two gradation data valuesare possible depending on the display position. For example, at thefield marked “12&14”, a gradation data value of 12 or 14 can be assigneddepending on the display position. Next, a specific example of thisdithering operation that involves an actual screen will be described.

[0066]FIG. 16 is a drawing for the purpose of describing operationsperformed by the dither processing module according to the firstembodiment of the present invention. FIG. 16 shows that the conversionfrom the gradation data to the reduced-color gradation data isequivalent to color reduction performed using dithering on 2×2 pixelunits. Another well-known color reduction method is the error diffusionmethod, and this method can also be used. The error diffusion methodprovides higher-quality color reduction compared to dithering but largercircuits are required. Thus, it would be desirable to use the differentmethods selectively according to application.

[0067] Next, the frame memory 105 stores the reduced-color gradationdata at an address based on the address transferred by the interface103. The frame memory 105 can be formed using standard SRAM. The timinggenerating module 106 generates timing signals described later and sendsthese signals to the frame memory 105 and the gradation voltage selector108. These timing signals include frame memory read control signals.Based on these control signals, reduced-color gradation data is readfrom the frame memory 105 one line at a time starting from the firstline on the screen. After the final line, the first line is read againand this operation is repeated. The timing for switching read lines issynchronized with the line signal provided by the timing generatingmodule 106. The timing for selecting the word line for the first line issynchronized with the frame signal provided by the timing generatingmodule 107. The specific timings for these are shown in FIG. 20,described later.

[0068]FIG. 17 is a circuit diagram for the purpose of describing thestructure of the gradation voltage generating module according to thefirst embodiment of the present invention. The gradation voltagegenerating module 107 is a circuit block that generates the gradationvoltages needed for converting gradation data to voltage levels. FIG. 17shows the internal structure of this block. In FIG. 17, VDH and VDD areprovided from outside. VDH is a reference voltage for generatinggradation voltages. VDD is a power source voltage for operationalamplifiers.

[0069] First, 64 levels of gradation voltages V0-V63 are generated byperforming resistance-division of the reference voltage VDH, and thesegradation voltages are buffered by operational amplifiers in a voltagefollower circuit. As shown in FIG. 17, the power supply to theoperational amplifiers is controlled by a switch 1701 and a switch 1702,which use the color reduction rate data as the control signal.

[0070]FIG. 18 is a drawing illustrating the operation of the gradationvoltage generating module according to the first embodiment of thepresent invention. The power supply states for the operationalamplifiers are shown for each of the color reduction rates. In FIG. 18,the crosshatched fields indicate where operational amplifier power isoff, and other fields indicate where power is on. Looking at the poweredoperational amplifier groups for each color reduction rate, thegradation voltage numbers that are buffered by these are the same as thereduced-color data groups shown in FIG. 15. This is because thecolor-reduction gradation data and the gradation voltage numbers areintentionally matched up. As a result, power can be supplied only to theoperational amplifiers to be used. Looking again at FIG. 15, thegradation voltages V0, V63 are used for all color-reduction rates, andthe other gradation values are levels that result from dividing up V0and V63 as evenly as possible. This was done to maximize the displaycontrast (dynamic range) for all the color-reduction rates. Thegradation voltage selector 108 is a circuit block that selects andoutputs one level out of the multiple gradation voltages based on thecolor-reduction gradation data.

[0071]FIG. 19 is a block diagram showing the structure of a gradationvoltage selector according to the first embodiment of the presentinvention. FIG. 20 is a timing chart for the purpose of describing theoperations performed by the gradation voltage selector according to thefirst embodiment of the present invention. FIG. 21 is a drawing for thepurpose of describing the operations of a selector according to thefirst embodiment of the present invention. The gradation voltageselector is formed from a latch module 1901 and a selector 1902. Thelatch module 1901 captures one line of color-reduction gradation dataoutput from the frame memory 105 using the line signal and outputs thisdata to the selector 1902. The selector 1902 selects one level out ofthe multiple gradation voltages based on the color-reduction gradationdata and the AC conversion signal.

[0072]FIG. 22 is an equivalent circuit illustrating the structure of thepixel module according to the first embodiment of the present invention.The pixel module is formed from three-terminal thin-film transistor TFTelements, a liquid crystal layer, and storage capacitors. The drainterminal of the thin-film transistor TFT element is connected to a dataline, the gate terminal is connected to a scan line, and the sourceterminal is connected to a liquid crystal cell and a storage capacitor.On the opposite side of the liquid crystal layer is a shared commonelectrode that is electrically connected to the liquid crystal layer.The other end of the storage capacitor is connected to the scan linefrom the previous level. One way to implement this structure is to formthe data lines and the scan lines on one of the inner surfaces of twotransparent substrates interposed by liquid crystal. The commonelectrode is formed tightly against the other inner surface. The pixelsin this embodiment use the “Cadd” structure, but it would also bepossible to use “Cst” structures, in which storage capacitor terminalsare connected to storage lines.

[0073] The display device driver circuit 101 of the present invention isconnected to the data lines of the pixel module 109 described above, anddesired gradation voltages are sent to the different data lines.Implementing an actual display device also requires a scan line drivermodule and a power supply circuit but these can be the same as existingcircuits. This is illustrated in FIG. 23.

[0074]FIG. 23 is a timing chart that illustrates the operationsperformed in the peripheral circuits according to the first embodimentof the present invention. For example, as shown in FIG. 23, the scanline driver module sends a “high” voltage to the first scan line in syncwith the frame signal. Then, “high” voltages are sent sequentially tothe following scan lines in sync with the frame signal. The switch from“high” voltage to “low” voltage takes place right before the switchingof gradation voltage, and the gradation voltage level corresponds to thegradation data for the particular scan line. The scan line driver modulecan also be easily implemented by using a shift-register circuit.

[0075] The common voltage, which is the voltage applied to the commonelectrode, has a waveform that is synchronized with an AC signal, andthis can be implemented with a circuit that adjusts the amplitude of theAC signal. The polarity of the voltage applied to the liquid crystal canbe considered as the polarity of the gradation voltage as seen from thecommon voltage, with the voltage to the liquid crystal being inverted insync with the AC signal. This operation is equivalent to a “commoninversion” system. While the first embodiment used a common inversionsystem as an example, the present invention is not restricted to this,and it would also be easy to use a dot inversion system or a rowinversion system. Also, this embodiment describes a TFT liquid crystaldisplay device, but the present invention is not restricted to this. Itwould also be possible to implement the present invention for otherdisplays that control display luminance with voltage levels, e.g.,organic EL displays. Also, it would be desirable to form the data linedriver module of the first embodiment as an LSI chip.

[0076] As described above, the first embodiment of the present inventionswitches the number of colors to be displayed based on color reductionrate data and stops driver circuits that are not needed for thedisplayed color count. As a result, the display device can consume lesspower. Also, the display can be made easier to use by providing ahigh-quality mode with little color reduction and a low-power mode withmore color reduction. For example, the display device and the displaydevice driver circuit of the present invention can be used in a mobiletelephone display device so that low-power mode with more colorreduction is used in stand-by mode while high-quality mode with lesscolor reduction is used when viewing video, natural images, and thelike. This selection can be performed automatically by having the CPUmonitor the operation state of the terminal device or it can beperformed manually by the user using terminal setting means or the like.

[0077] Next, a second embodiment of the present invention will bedescribed using FIG. 24 through FIG. 33. In the first embodiment of thepresent invention described above, dithering is used to provide colorreduction. In contrast, the second embodiment of the present inventionuses FRC to reduce colors. FRC is an acronym for “frame rate control”.In FRC, existing colors are combined both spatially and temporally togenerate intermediate colors, as shown in FIG. 25. Compared to thedithering method described above, intermediate colors can be expressedwithout sacrificing resolution.

[0078]FIG. 24 is a block diagram showing the structure of a displaydevice driver circuit according to the second embodiment of the displaydevice of the present invention. FIG. 25 is a drawing illustratingprinciples involved in an FRC system according to the second embodimentof the present invention. FIG. 26 is a drawing illustrating colorreduction rate data according to the second embodiment of the presentinvention. FIG. 24 shows a data line driver circuit 2401 and an FRCprocessing module 2402. The other blocks are identical to those from thefirst embodiment of the present invention and are assigned the samenumerals. The major difference between the data line driver circuit 2401of this embodiment and the data line driver circuit 101 from the firstembodiment of the present invention is that in the FRC system, the readoperations from the frame memory 105 and color reduction operations mustbe synchronized in order to switch displayed images for each frameinterval (i.e., the scan time for a single screen).

[0079] Thus, the FRC processing module 2402 performs FRC processingbased on the received color reduction rate data for all gradation datain the lines that are read sequentially from the frame memory 105, andthe results are output to the gradation voltage selector 108. In thisembodiment, the color reduction rate data is a 1-bit value thatindicates one of two types of color reduction rates, and, as shown inFIG. 26, this value indicates the number of bits out of the RGBgradation data (6 bits each) on which to perform FRC processing.

[0080]FIG. 27 is a block diagram showing the structure of an FRCprocessing module according to the second embodiment of the presentinvention. FIG. 28 is a block diagram showing the structure of an FRCsignal generating module according to the second embodiment of thepresent invention. FIG. 29 is a timing chart illustrating the operationsperformed by the FRC signal generating module according to the secondembodiment of the present invention. FIG. 30 is a drawing illustratingthe operations performed by the FRC signal generating module accordingto the second embodiment. FIG. 31 is a block diagram showing thestructure of a data conversion module according to the second embodimentof the present invention. FIG. 27 shows an FRC signal generating module2701 and a data conversion module 2702. As shown in FIG. 28, the FRCsignal generating module 2701 generates two types of FRC signals from aframe signal and a line signal transferred from the timing generatingmodule 106. The timing charts for these are shown in FIG. 29.

[0081] As shown in FIG. 27, these two FRC signals are connected to dataconversion modules in an alternating manner. The FRC signal valuescorresponding to the actual screen are arranged as shown in FIG. 30.This is equivalent to the pattern of combining existing colors shown inFIG. 25. As shown in FIG. 31, the data conversion module 2702 is formedfrom a bit operation module A 3101, a subtractor 3102, and a bitoperation module B 3103. The bit operation module A 3101 is converted to6 bits by adding a “0” to the FRC signal, but how the “0” is addeddiffers depending on the color reduction rate data.

[0082]FIG. 32 is a drawing illustrating the operations of the bitoperation module A according to the second embodiment of the presentinvention. FIG. 33 is a drawing describing the operation of the bitoperation module B according to the second embodiment. FIG. 32illustrates how the “0” is added to the FRC signal to form 6 bits asdescribed above. The object of this bit operation is to make subtractionoperations easier at the next step. Also, the output value of the bitoperation module A is changed depending on the highest bit of thegradation data so that the subtraction results do not come out negative.

[0083] Next, the subtractor 3102 subtracts the output from the bitoperation module A from the gradation data. Then, the bit operationmodule B 3103 rearranges the gradation data bits based on the colorreduction rate data, as shown in FIG. 33, and the results are output asthe reduced-color gradation data.

[0084] By performing this FRC operation all at once for an entire lineof gradation data, FRC color reduction based on 2×2 pixel units ispossible. In this embodiment, FRC processing is performed on the lowestbit in the 6-bit gradation data. The present invention is not restrictedto this, however, and it would of course also be possible to apply FRCto the two lowest bits.

[0085] Other blocks execute functions identical to the blocks shown inthe first embodiment of the present invention, so overlappingdescriptions will be omitted.

[0086] As in the first embodiment of the present invention, the secondembodiment of the present invention described above switches the numberof colors to be displayed based on color reduction rate data and stopsdriver circuits that are not needed for the displayed color count. As aresult, the display device can consume less power. Also, the display canbe made easier to use by providing a high-quality mode with little colorreduction and a low-power mode with more color reduction. Furthermore,since FRC is used for color reduction, intermediate colors can beexpressed without sacrificing resolution.

[0087]FIG. 34 is a block diagram showing the structure of a displaydevice driver circuit according to the second embodiment of the presentinvention. As shown in FIG. 34, it is possible to implement a displaydevice driver circuit equipped with both dither processing and FRCprocessing. In this case, it would be possible to use just ditherprocessing or FRC processing or to use both in combination. This can beachieved by having the color reduction rate data provided separately forboth dither processing and FRC processing. Furthermore, the presentinvention is not restricted to transferring color reduction data fromthe CPU, and it would also be possible to use jumper settings. Also, asshown in FIG. 35, it would be possible to select between CPU transferand jumper settings.

[0088] Next, a third embodiment of the present invention will bedescribed using FIG. 36 through FIG. 41. In the first and the secondembodiments of the present invention, display signals are transferred tothe CPU and the display device driver circuit is equipped with its ownframe memory. This structure is frequently used in compact displays suchas mobile phone displays. In contrast, the third embodiment of thepresent invention described below transfers display signals from adedicated graphic controller and the display device driver circuit isnot equipped with frame memory. This structure is frequently used inlarge displays.

[0089]FIG. 36 is a block diagram showing the structure of a displaydevice driver circuit according to the third embodiment of the displaydevice of the present invention. FIG. 37 is a timing chart for inputsignals in the third embodiment of the present invention. FIG. 36 showsa data line driver module 3601, a graphic controller 3602, a ditherprocessing module 3603, and a gradation voltage selector 3604. Thegradation voltage generating module 107 is identical to the gradationvoltage generating modules from the first embodiment and the secondembodiment of the present invention.

[0090] The graphic controller 3602 outputs gradation data and displaysync signals shown in FIG. 37 to serve as “raster scan” display signals.The dither processing module 3603 receives these display sync signals,gradation data, and color reduction rate data, applies dithering toperform color reduction on the gradation data, and outputs thereduced-color gradation data. The color reduction rate data here can beprovided from an external CPU, set from jumpers, set from manualswitches on the device, or the like.

[0091]FIG. 38 is a block diagram showing the structure of a ditherprocessing module according to the third embodiment of the presentinvention. FIG. 39 is a block diagram showing the structure of a dithersignal generating module according to the third embodiment of thepresent invention. FIG. 38 shows a dither signal generating module 3801.Data conversion modules 802-804 are identical to those from the firstembodiment of the present invention. As shown in FIG. 39, the dithersignal generating module 3801 includes a vertical position counter 3901,a horizontal position counter 3902, and a decoder 3903. The verticalposition counter 3901 is cleared during the “high” interval of the framesignal and counts up in sync with the leading edges of the effectiveinterval signals. The horizontal position counter 3902 is cleared duringthe “high” interval of the line signal and counts up in sync with theleading edges of the dot clock when the effective interval signal is“high”.

[0092] As a result, the outputs from these counters are equivalent tothe vertical address and the horizontal address shown in FIG. 9.Furthermore, the decoder 3903 at the next state generates the four typesof dither signals shown in FIG. 9 based on the received counter values.Furthermore, since the data conversion module is identical to the onefrom the first embodiment of the present invention, reduced-colorgradation data identical to that of the first embodiment is output fromthe dither processing module 3603. The gradation voltage generatingmodule 107 has the same structure and performs the same operations asthat of the first embodiment of the present invention, so itsdescription will be omitted here.

[0093]FIG. 40 is a block diagram showing the structure of a gradationvoltage selector according to the third embodiment of the presentinvention. FIG. 41 is a timing chart illustrating the operationsperformed by the gradation voltage selector of the third embodiment ofthe present invention. In FIG. 40, the gradation voltage selector 3604is a circuit block that captures and synchronizes reduced-colorgradation data transferred for each RGB pixel, selects a gradationvoltage level from multiple gradation voltages based on the gradationlevel, and outputs the result. As shown in FIG. 40, it includes acapture latch module 4001, a sync latch module 4002, and a selector4003.

[0094] When the trailing edge of the line signal is cleared and theeffective interval signal is “high”, the capture latch module 4001captures one row of reduced-color gradation data at a time in sync withthe leading edge of the dot clock. The sync latch module 4002 capturesthe reduced-color gradation data output from the capture latch module4001 in sync with the leading edge of the line signal and outputs theresult to the selector 4003. The selector 4003 selects one out ofmultiple gradation voltage levels based on the reduced-color gradationdata and the AC conversion signal. The operations performed by theselector 4003 are identical to those of the selector 1902 from the firstembodiment of the present invention. FIG. 41 shows the operation timingof the gradation voltage selector 3604.

[0095] As in the first embodiment of the present invention, the thirdembodiment of the present invention described above switches the numberof colors to be displayed based on color reduction rate data and stopsdriver circuits that are not needed for the displayed color count. As aresult, the display device can consume less power. Also, the display canbe made easier to use by providing a high-quality mode with little colorreduction and a low-power mode with more color reduction. Furthermore,the display device can be connected to a graphic controller and a rasterscan signal can be sent to the display device. Also, dithering was usedin the third embodiment, but it goes without saying that FRC processingcan be performed as well.

[0096] Next, a fourth embodiment of the present invention will bedescribed using FIG. 42 through FIG. 44. In the fourth embodiment of thepresent invention, the display device driver circuit from the firstthrough the third embodiments of the present invention are implementedin a display device. FIG. 42 and FIG. 43 show structures where a displaydevice driver circuit is equipped with its own frame memory. FIG. 44shows a structure where the display device driver circuit is notequipped with frame memory.

[0097]FIG. 42 is a block diagram showing the structure of a displaydevice according to the fourth embodiment of the present invention. FIG.43 is a block diagram showing the structure of a display deviceaccording to the fourth embodiment of the present invention. FIG. 44 isa block diagram showing the structure of a display device according tothe fourth embodiment of the present invention.

[0098]FIG. 42 shows a display device 4201, which broadly includes a dataline driver module 4202, a scan line driver module 4203, a power supply4204, and an pixel module 109. The data line driver module 4202 issimilar to the data line driver module 101 from the first embodiment ofthe present invention, but differs in that it is equipped with a dataregister 4205. The data register 4205 is an element that stores variousdriver parameters transferred from the CPU. These parameters aretransferred to the different circuit blocks.

[0099] Examples of these parameters include the drive line count, theframe frequency, and the like. The color reduction rate data, which ischaracteristic of the present invention, is also included in theseparameters. An example of a method for transferring parameters from theCPU is to have the transfer method illustrated in FIG. 3 shared betweenthe frame memory and the data register. In this case, an unused bit(e.g., D17) in the addressing cycle shown in FIG. 4 can be used as aframe memory/data register identification bit.

[0100] The scan line driver module 4203 is a circuit block that drivesthe scan line for the pixel module 109. The output signal waveform isthe same as that of the scan voltage shown in FIG. 23. The power supply4204 outputs the common voltage shown in FIG. 23 and also generatespower-supply voltage needed by the display device of the presentinvention and sends the output to the different circuit blocks. Thisoperation can be achieved using means for stepping up a system powersupply provided from outside and means for adjusting the stepped-upvoltage. The control information for voltage adjustment and the like aretransferred from the data register 4205. The pixel module 109 has thesame structure and operates in the same manner as that of the firstembodiment of the present invention, so its description will be omittedhere.

[0101] As described above, FIG. 43 shows an FRC processing module addedto the data line driver circuit in the display device, and FIG. 44 showsa data line driver circuit without frame memory. The correspondingoperations consist of the addition of the scan line driver circuit andthe power supply to the data line driver circuits shown in FIG. 42 andFIG. 36, so their detailed descriptions will be omitted here.

[0102] As in the first through the third embodiments of the presentinvention, the fourth embodiment of the present invention describedabove switches the number of colors to be displayed based on colorreduction rate data and stops driver circuits that are not needed forthe displayed color count. As a result, the display device can consumeless power. Also, the display can be made easier to use by providing ahigh-quality mode with little color reduction and a low-power mode withmore color reduction.

[0103] The present invention is not restricted to the structuredescribed in the claims and in the embodiments above. Variousmodifications may be effected without departing from the spirit of theinvention.

What is claimed:
 1. A display device comprising: a pixel circuit inwhich a plurality of intersecting data lines and scan lines are formed,pixels being formed near said intersections; a data line driverincluding a gradation voltage generating circuit formed from a pluralityof voltage level generating circuits, using gradation data representingcolor concentration of an original image received from a higher-leveldevice to select a gradation voltage generated by said plurality ofvoltage level generating circuits, and using an internally generateddisplay sync signal to output said selected gradation voltages a line ata time to said data lines; a scan line driver using said display syncsignal to output scan voltages to said scan lines for sequentialselection of said scan lines; and a power supply circuit generating saidgradation voltages, said scan voltages, and reference potentials neededto drive said display device, wherein said data line driver reducescolor count information size in said gradation data received from saidhigher-level device based on said color reduction rate data and halts aportion of said plurality of voltage level generating circuits driversbased on said color reduction rate data.
 2. A display device asdescribed in claim 1 wherein said data line driver reduces said colorcount information size in said gradation data by dithering and/or FRCprocessing.
 3. A display device as described in claim 1 wherein saidcolor reduction rate data values include
 0. 4. A display device asdescribed in claim 1 wherein said gradation voltage has a dynamic rangethat is fixed regardless of said color reduction rate data value.
 5. Adisplay driver comprising: a memory storing gradation levelsrepresenting color concentrations of an original image provided by ahigher-level device; a timing generating circuit internally generating adisplay sync signal based on control data provided by said higher-leveldevice; a gradation voltage generating circuit generating a saidgradation voltages having a plurality of levels; a gradation voltageselector selecting one level out of said plurality of gradation voltagesgenerated by a plurality of voltage level generating circuits of saidgradation voltage generating circuit based on gradation data read fromsaid frame memory, and outputting said selected gradation voltages oneline at a time; and a color reduction processing circuit reducing colorcount information size of said gradation data based on said colorreduction rate data; wherein said gradation voltage generating circuithalts output of said gradation voltage levels made unnecessary fordisplaying as a result of said reduction of said color count informationsize in said gradation data.
 6. A display driver as described in claim 5wherein: said higher-level device is a CPU, and gradation data,addressing information indicating display positions, and the like arereceived from said CPU; and said color reduction rate data is receivedfrom said CPU via data transfer or manual settings or jumper settings.7. A display driver as described in claim 5 wherein: said higher-leveldevice is a graphic controller, said graphic controller transferringdisplay sync signals and gradation data for raster scanning; and saidcolor reduction rate data is received from said CPU via data transfer,manual settings, jumper settings, or the like.
 8. A display driver asdescribed in claim 5 wherein said gradation voltage generating circuithalts output of voltage levels not needed for displaying by shutting offbias current to operational amplifies performing buffering of saidgradation voltages.
 9. A display driver as described in claim 5 whereinsaid color reduction rate data values include
 0. 10. A display driver asdescribed in claim 5 wherein said gradation voltage has a dynamic rangethat is fixed regardless of said color reduction rate data value.